This invention relates to semiconductor memory devices and more particularly to an improved sense amplifier for an MOS random access read/write memory.
Semiconductor memory devices of the type made by the N-channel silicon-gate MOS process and employing one transistor dynamic cells are now the most widely used in computers and digital equipment. A continuing problem in these devices is the sense amplifier which must detect the small change in voltage on a digit line caused by a cell being addressed. As the number of cells on a digit line increases and the cell size decreases, the ratio of the storage capacitance to the digit line capacitance decreases and so the voltage change decreases. The trend toward use of 5 V. power supplies rather than 12 V. also reduces the signal level. These factors make the performance of the sense amplifier more critical. Also, the continuing trend toward higher speeds and lower power dissipation place additional constraints on the sense amplifier design. Examples of prior sense amplifiers are disclosed in U.S. Pat. No. 3,909,631, and 4,050,061 issued to N. Kitagawa, No. 4,081,701 issued to White, McAdams and Redwine, all assigned to Texas Instruments, as well as articles in Electronics Magazine, Sept. 13, 1973 at pp. 116-121, Feb. 19, 1976 at pp. 116-121, and May 13, 1976 at pp. 81-86 and U.S. Pat. No. 4,061,999. The prior sense amplifiers have not been adequate for new designs of MOS RAMS of very high density--64K bits, operating on a single 5 V. supply with access times of 100 to 150 nsec. or faster.
It is the principal object of this invention to provide an improved sense amplifier for a high speed MOS RAM, particularly for a very dense array of one-transistor cells. Another object is to provide a sense amplifier which may be used in a dense MOS memory which operates from a low voltage supply such as 5 V.